It appears that any offset value would be the same for any ADC channel used
Something which id like to see the code to over come when you goto ground the AD input to get the offset reading then then apply the voltage, The reading for the same ADC voltage using the 16f1947 was about 950dec, so other settings are need to to get the correct value, but which ones ill find out as i play with the test program.Īlso if you are getting the hardware there was new errata posted a last week 10/1/14 on this chip family, relating to the adc error offset which is need to be allowed for if your VDD is above 3v3, Was surprised to see that the ADCin command set the TRESA to inputīut that sample compiles and gives a result on the hardware ( 214dec) for a 2.9v applied voltage to adc4
Thought id still need to set TRESA input, adc clock ,Tad setting, adcon1, Avss, Avdd, Vref, etc before any meaning full input would be produced Your right, i was just taking adc part out of large program and not gone and make it separate most simple program to sort, with a new cpuīelieve it or not this is the first time on the forum that any sample config was put up for the 18f67k22, 18f87k22 I will have access to a real 67K22 tomorrow. ' Bit 1 - Go/_done status flag - 1 = Go do ADC / 0 = Done ADC, Bit 0 = Enable ADC = 1 / 0 = Disable ADCĪDCIN 4 ,Value ' Leave out for Rev 2 of 16F1947 - Read PortA.5 value into variable, this applies the fixed voltage ref (via ADCON0,ADCON1,FVRCON)Ĭode: -ĬONFIG INTOSCSEL = HIGH LF-INTOSC in High-power mode during SleepĬONFIG SOSCSEL = HIGH High Power SOSC circuit selectedĬONFIG FOSC = INTIO2 Internal RC oscillatorĬONFIG BOREN = SBORDIS Enabled in hardware, SBOREN disabledĬONFIG BORPWR = ZPBORMV ZPBORMV instead of BORMV is selectedĬONFIG WDTEN = SWDTDIS WDT enabled in hardware SWDTEN bit disabledĬONFIG MSSPMSK = MSK7 7 Bit address masking modeĬONFIG MCLRE = ON MCLR Enabled, RG5 DisabledĬONFIG BBSIZ = BB1K 1K word Boot Block size ' Bit 2-0 = Analoge Neg Ch Select ( Differential measurement ) ' Bit3 - VNCFG- 1= External Vref-, 0= AVSS Vref/A , ' note: ADCON0 - channel selection done in routines using the required channelĪDCON1 = %00000000 ' bit 7-6 = TRIGSEL 11= triger from RTCC, 10 = trigger from timer1 ,01 = trigger from CTMU, 00= trigger from ECCP2 ' -ADC Settings, routines and Varaiables. TRISA = %00100000 ' setup Port A input=1,output=0 for I/O pins, set input for RA5 ' - Setup port A Variables & directions -ĪNCON0.0 = 0 ' Set PortA:0 Analog / Digital allocation - 0 = digital ,1 analog - ANSEL0ĪNCON0.1 = 0 ' Set PortA:1 Analog / Digital allocation - 0 = digital ,1 analog - ANSEL1ĪNCON0.2 = 0 ' Set PortA:2 Analog / Digital allocation - 0 = digital ,1 analog - ANSEL2ĪNCON0.3 = 0 ' Set PortA:3 Analog / Digital allocation - 0 = digital ,1 analog - ANSE元ĪNCON0.4 = 1 ' Set PortA:5 Analog / Digital allocation - 0 = digital ,1 analog - ANSEL4 Set RA5 (AN4/ ANSEL4) to be analog input for V-Mon ' bit5 0= toggle mode diabled 1= enabled bit4 single pulse mode 1- en 0= dis, bit 2 -status bit,1-0 - gate source selĭEFINE OSC 32 ' Timing referance for pause, pauseus commandsĭEFINE ADC_BITS 12 ' Number of bits in ADCIN result - Required for adcin commandĭEFINE ADC_CLOCK 5 ' fosc/32 0.8uS 32MhzĭEFINE ADC_SAMPLEUS 20 ' ADC sampling time in microseconds - Required for adcin command T1GCON = %00000000 ' Timer 1 Gate Control bit7 0= counts regardless of gate 1 = gates in use, bit6 gate active when 1= High ,0=low ' bit5-4 = TMR1 prescale 11= 1:8 ,bit3=0 LP off,bit2=1 no sync ext CLK ,bit1= 0 n/a,Bit0=0 Timer 1 on/off
Code: HLVDCON = $00 'Turn off HIGH /LOW Voltage Detect Module